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july 2012 FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMS3620S rev.c1 FDMS3620S powertrench ? powerstage 25v asymmetric dual n-channel mosfet features q1: n-channel ? max r ds(on) = 4.7 m at v gs = 10 v, i d = 17.5 a ? max r ds(on) = 5.5 m at v gs = 4.5 v, i d = 16 a q2: n-channel ? max r ds(on) = 1.0 m at v gs = 10 v, i d = 38 a ? max r ds(on) = 1.2 m at v gs = 4.5 v, i d = 35 a ? low inductance packaging shortens rise/fall times, resulting in lower switching losses ? mosfet integration enables optimum layout for lower circuit inductance and reduced switch node ringing ? rohs compliant general description this device includes two specialized n-channel mosfets in a dual pqfn package. the switch node has been internally connected to enable easy placement and routing of synchronous buck converters. the contro l mosfet (q1) and synchronous syncfet (q2) have been designed to provide optimal power efficiency. applications ? computing ? communications ? general purpose point of load ? notebook vcore 4 3 2 1 5 6 7 8 q 1 q 2 power 56 g1 d1 d1 d1 g2 s2 s2 s2 d1 phase (s1/d2) s2 s2 s2 g2 d1 d1 d1 g1 top bottom phase pin 1 pin 1 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 25 25 v v gs gate to source voltage (note 4) 12 12 v i d drain current -continuous (package limited) t c = 25 c 30 49 a -continuous (silicon limited) t c = 25 c 76 211 -continuous t a = 25 c 17.5 1a 38 1b -pulsed 70 150 e as single pulse avalanche energy (note 3) 29 135 mj p d power dissipation for single operation t a = 25 c 2.2 1a 2.5 1b w power dissipation for single operation t a = 25 c 1.0 1c 1.0 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 57 1a 50 1b c/w r ja thermal resistance, junction to ambient 125 1c 120 1d r jc thermal resistance, junction to case 3.0 1.7 device marking device package reel size tape width quantity 08od 06od FDMS3620S power 56 13 ? 12 mm 3000 units
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMS3620S rev.c1 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 25 25 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 12 16 mv/c i dss zero gate voltage drain current v ds = 20 v, v gs = 0 v q1 q2 1 500 a a i gss gate to source leakage current v gs = 12/-8 v, v ds = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1 ma q1 q2 0.8 1.1 1.2 1.3 2.0 2.2 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 -4 -4 mv/c r ds(on) drain to source on resistance v gs = 10 v, i d = 17.5 a v gs = 4.5 v, i d = 16 a v gs = 10 v, i d = 17.5 a,t j =125 c q1 3.8 4.4 5.4 4.7 5.5 7.0 m v gs = 10 v, i d = 38 a v gs = 4.5 v, i d = 35 a v gs = 10 v, i d =38 a ,t j =125 c q2 0.8 0.9 1.1 1.0 1.2 1.5 g fs forward transconductance v ds = 5 v, i d = 17.5 a v ds = 5 v, i d = 38 a q1 q2 100 271 s c iss input capacitance q1: v ds = 13 v, v gs = 0 v, f = 1 mhz q2: v ds = 13 v, v gs = 0 v, f = 1 mhz q1 q2 1570 6861 pf c oss output capacitance q1 q2 448 1828 pf c rss reverse transfer capacitance q1 q2 61 232 pf r g gate resistance q1 q2 0.1 0.1 0.4 0.6 3.3 3.5 t d(on) turn-on delay time q1: v dd = 13 v, i d = 17.5 a, r gen = 6 q2: v dd = 13 v, i d = 38 a, r gen = 6 q1 q2 7 14 ns t r rise time q1 q2 2 7 ns t d(off) turn-off delay time q1 q2 23 41 ns t f fall time q1 q2 2 5 ns q g total gate charge v gs = 0 v to 10 v q1 v dd = 13 v, i d = 17.5 a q2 v dd = 13 v, i d = 38 a q1 q2 26 106 nc q g total gate charge v gs = 0 v to 4.5 v q1 q2 12 50 nc q gs gate to source gate charge q1 q2 3.3 12.9 nc q gd gate to drain ?miller? charge q1 q2 2.7 12 nc
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMS3620S rev.c1 electrical characteristics t j = 25 c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source to drain diode forward voltage v gs = 0 v, i s = 17.5 a (note 2) v gs = 0 v, i s = 38 a (note 2) q1 q2 0.8 0.8 1.2 1.2 v t rr reverse recovery time q1 i f = 17.5 a, di/dt = 100 a/ s q2 i f = 38 a, di/dt = 300 a/ s q1 q2 23 38 ns q rr reverse recovery charge q1 q2 9 54 nc notes: 1.r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2 pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. q1 :e as of 29 mj is based on starting t j = 25 o c; n-ch: l = 0.3 mh, i as = 14 a, v dd = 23 v, v gs = 10 v. 100% test at l= 0.1 mh, i as = 20 a. q2: e as of 135 mj is based on starting t j = 25 o c; n-ch: l = 0.3 mh, i as = 30 a, v dd = 23 v, v gs = 10 v. 100% test at l= 0.1 mh, i as = 44 a. 4. as an n-ch device, the negative vgs rating is for low duty cycle pulse occurrence only. no continuous rating is implied. a. 57 c/w when mounted on a 1 in 2 pad of 2 oz copper b. 125 c/w when mounted on a minimum pad of 2 oz copper c. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 120 c/w when mounted on a minimum pad of 2 oz copper
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMS3620S rev.c1 typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. 0.0 0.3 0.6 0.9 1.2 1.5 0 10 20 30 40 50 60 70 v gs = 2.5 v v gs = 3 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 10203040506070 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 2.5 v v gs = 4.5 v v gs = 3 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i d = 17.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 2345678910 0 4 8 12 16 20 t j = 125 o c i d = 17.5 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 50 60 70 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 70 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMS3620S rev.c1 figure 7. 0 4 8 12 16 20 24 28 0 2 4 6 8 10 i d = 17.5 a v dd = 15 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 13 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 50 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 r t jc = 3.0 o c/w v gs = 4.5 v limited by package v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100 0.01 0.1 1 10 100 100 p s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c 10s figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 1000 single pulse r t ja = 125 o c/w p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMS3620S rev.c1 figure 13. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMS3620S rev.c1 typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 14. on-region characteristics figure 15. normalized on-resistance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics figure 19. source to drain diode forward voltage vs source current 0 0.3 0.6 0.9 0 30 60 90 120 150 v gs = 3 v v gs = 3.5 v v gs = 10 v v ds , drain to source voltage (v) i d , drain current (a) v gs = 2.5 v v gs = 4.5 v pulse duration = 80 s duty cycle = 0.5% max 0 30 60 90 120 150 0 1 2 3 4 5 6 v gs = 3.5 v v gs = 3 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 2.5 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 38 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 1 2 3 4 5 t j = 125 o c i d = 38 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m pulse duration = 80 s duty cycle = 0.5% max 1.0 1.5 2.0 2.5 3.0 0 30 60 90 120 150 t j = 150 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMS3620S rev.c1 typical characteristi cs (q2 n-channel) t j = 25c unless otherwise noted figure 20. gate charge characteristics figure 21. capacitance vs drain to source voltage figure 22. unclamped inductive switching capability f i g u r e 2 3 . m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 2 4 . f o r w a r d b i a s s a f e operating area figure 25. single pulse maximum power dissipation 0 20406080100120 0 2 4 6 8 10 i d = 38 a v dd = 15 v v dd = 13 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 10 v 0.1 1 10 30 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.001 0.01 0.1 1 10 100 1000 1 10 100 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 25 50 75 100 125 150 0 30 60 90 120 150 180 210 v gs = 4.5 v r jc = 1.7 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 100 us 1 ms 1 s 10 ms dc 10 s 100 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ja = 120 o c/w t a = 25 o c 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 10000 single pulse r ja = 120 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (s)
typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 26. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.0001 0.001 0.01 0.1 1 single pulse r t ja = 120 o c/w note 1d duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (s) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 9 www.fairchildsemi.com FDMS3620S rev.c1
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 10 www.fairchildsemi.com FDMS3620S rev.c1 syncfet schottky body diode characteristics fairchild?s syncfet process emb eds a schottky diode in parallel with powertrench mosfet. th is diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 27 shows the reverse recovery characteristic of the FDMS3620S. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. 0 50 100 150 200 250 300 350 -5 0 5 10 15 20 25 30 35 40 45 di/dt = 300 a/ s current (a) time (ns) 0 5 10 15 20 25 10 -6 10 -5 10 -4 10 -3 10 -2 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v) typical characteristics (q2 n-channel) figure 27. FDMS3620S syncfet body diode reverse recovery characteristic figure 28. syncfet body diode reverse leakage versus drain-source voltage
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 11 www.fairchildsemi.com FDMS3620S rev.c1 dimensional outlin e and pad layout c l l c pkg pkg 5.10 4.90 6.10 5.90 c 3.00 2.80 3.81 1.02 0. 82 top view side view bottom view 14 85 123 4 876 0.10 cab 0.05 c 2.25 2.05 5 0.58 0.38 notes: unless otherwise specified a) does not fully conform to jedec registration, mo-240, issue b dated 10/2009. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) it is recommended to have no traces or vias within the keep out area. f) drawing file name: pqn08erev4. see det ail a detail a (scale: 2x) 0.05 0.00 0.30 0.20 0.08 c pin #1 ident may appear as optional seating plane 0.10 c 1. 10 0.90 recom mende d land patt ern 0.65 typ 1 2 3 4 5 6 7 8 1.27 1.32 1.12 a 0.10 c 2x b 0.10 c 2x 0.00 0.00 1.60 2.52 1.21 2.31 1.18 1. 27 typ 2.00 2.15 0.63 0. 63 0.59 3.18 4.00 c l c l 0.51 0.31 0.58 0.38 2.13 3.15 0.35 0.70 0.50 3. 90 3. 70 0.44 0.24 6x 0.71 0.61 keep out area 5.10 4.16
FDMS3620S powertrench ? powerstage ?2012 fairchild semiconductor corporation 12 www.fairchildsemi.com FDMS3620S rev.c1 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions , specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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* serdes? uhc ? ultra frfet? unifet? vcx? visualmax? voltageplus? xs? ? ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product t hat is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing de lays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages cu stomers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our custom ers to do their part in stopping this practice by buying direct or from authorized distributors. rev. i61 tm ?

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